Monthly Archives: May 2015

Field-Programmable Gate Array (FPGA)

The design-layout process of trace routing a printed circuit board requires device, technology, and material knowledge, plus the design talent and competency to fit a set of connection-dependent devices on to a board using one or two sides and two or more trace layers.

It is a highly iterative search, test, layout, and refinement process to converge on final layout:

  • A Looping or cyclic process
  • Clearly identifiable coupled-activity where interrelationships and information associations determine tactics, next steps, and outcome
  • Can estimate duration, or a range, and with parameters for revising first converged solution (assumption: low frequency designs)
  • RF designs will take much longer (physical layout critical)

Performance: circuit characteristics, board size, duration, and quality are based on designer skill, domain knowledge, and experience.

FPGA Coupling May 2015

Most interesting is the layout process where an FPGA is part of the schematic and board design. The majority of pins on an FPGA can be software defined and allocated at load time. This results in an even more highly-coupled and interdependent process with integrated change between schematic and physical layout as concurrent decisions on schematic, layout, and device placement are made during the board design.